A Chinese Chip Design Takes Aim At The GPU Moat

A team at Peking University published in National Science Review an architecture that optically links commodity FPGA chips via silicon-photonic transceivers, reporting roughly a 100x distributed-inference speedup at about one-ninth the compute resources. The design deliberately uses FPGAs, which fall outside the advanced-chip export controls — sanctions-resistant by choice.

Contests Layer 2. The capex case rests on compute scarcity being the binding constraint; if inference — where most production compute is spent — gets materially cheaper per unit, the demand curve justifying $1T+ of buildout weakens and the hardware-scarcity moat narrows. Two honest limits keep this from being a thesis-killer: it is a lab result, not a deployed product, and the road from a journal paper to inference-at-scale runs in years, not weeks; and the headline figures are relative to a distributed-FPGA baseline, not to a GPU cluster, so they do not convert cleanly into "90% less GPU demand." It also hits inference, not training — and the memory trade is training-bid, so the read-through there is partial. What it clearly is: another instance of the decoupling pattern, where each US export tightening is met by a Chinese architecture that routes around the controlled hardware.